Gated clocks in RT-synthesis and simulation

The paper discusses several alternatives for dealing with the simulation mismatch resulting from partially gating clocks in RT-descriptions. Currently synthesizable approaches as clock delta balancing and simulation time delay of combinatorial assignments are first discussed. Local clock gate descriptions based on wait statements and global clock gate descriptions based on guards are then presented. Finally, an extension of the VHDL port map towards type conversion functions with more than one (signal)-parameter is proposed