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On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

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2 Author(s)
Tai-Ho Wang ; Production & Technol. Div., Sunplus Technol. Co. Ltd., Hsinchu, Taiwan ; Ming-Dou Ker

A novel on-chip ESD protection design using polysilicon diodes for a smart card application is reported in this paper. By adding an efficient V/sub DD/-to-V/sub SS/ clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original /spl sim/300 V to become /spl ges/3 kV. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimization of the polysilicon diodes for both smart card application and on-chip ESD protection design.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000

Date of Conference:

26-28 Sept. 2000