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Parallelization methodology for video coding-an implementation on the TMS320C80

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3 Author(s)
Kwong-Keung Leung ; Dept. of Electr. & Electron. Eng., Hong Kong Univ., China ; Yung, N.H.C. ; Cheung, P.Y.S.

This paper presents a parallelization methodology for video coding based on the philosophy of hiding as much communications by computation as possible. It models the task/data size, processor cache capacity, and communication contention, through a systematic decomposition and scheduling approach. With the aid of Petri-nets and task graphs for representation and analysis, it employs a triple buffering scheme to enable the functions of frame capture, management, and coding to be performed in parallel. The theoretical speedup analysis indicates that this method offers excellent communication hiding, resulting in system efficiency well above 90%. To prove its practicality, a H.261 video encoder has been implemented on a TMS320C80 system using the method. Its performance was measured, from which the speedup and efficiency figures were calculated. The only difference detected between the theoretical and measured data is the program control overhead that has not been accounted for in the theoretical model. Even with this, the measured speedup of the H.261 is 3.67 and 3.76 on four parallel processors (PPs) for QCIF and 352×240 video, respectively, which correspond to a frame rate of 30.7 and 9.25 frames per second, and system efficiency of 91.8% and 94%, respectively. This method is particularly efficient for platforms with a small number of parallel processors

Published in:

Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:10 ,  Issue: 8 )

Date of Publication:

Dec 2000

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