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Impact of level 2 cache and memory subsystem on the scalability of clusters of small-scale SMP servers

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4 Author(s)

This paper presents a performance study of two commodity clusters built from two models of Dell PowerEdge servers. Both clusters have eight servers interconnected by GigaNet for fast message passing and by Fast Ethernet for Network File System (NFS) traffic. The two server models are different in processors, level 2 (L2) cache, speed of front-side bus (FSB), chipsets and memory subsystem. They represent generic servers from two generations of Intel-based architecture. In this study, we use well-known benchmark programs to understand how they perform for computation-intensive applications. We first study their performance in stand-alone environment to unveil the performance characteristic of a compute node. We further explore their aggregated performance when they are used in a cluster environment. We are particularly interested in their scalability, per-processor performance degradation due to memory contention and inter-process communications and the correlation between results from different benchmark programs. We found that L2 cache and memory subsystem have significant impact on computation-intensive parallel applications such as the NAS Parallel Benchmark (NPB) programs. For configurations with a large number of processors (or multiple processors per compute node), some of NPB programs perform better on platform with larger global L2 cache, even though the platform has slower processors, FSB and memory components

Published in:

Cluster Computing, 2000. Proceedings. IEEE International Conference on

Date of Conference:

2000

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