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Modeling and simulation of integrated capacitors for high frequency chip power decoupling

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3 Author(s)
E. Diaz-Alvarez ; Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA ; J. P. Krusius ; F. Kroeger

Power and ground decoupling is typically accomplished using a hierarchy of discrete capacitors spread throughout the power distribution network. Many of the limitations of discrete decoupling capacitors can be overcome with integrated capacitors. A modeling approach for integrated capacitors based on the partial-element-equivalent-circuit (PEEC) formulation is presented. This approach has been applied to 3M C-ply, a flexible planar integrated capacitor technology that can be laminated into multilayer substrates, such as printed wiring boards. The decoupling capability of 3M C-Ply technology for chip power distribution has been compared with conventional surface-mount technology (SMT)

Published in:

IEEE Transactions on Components and Packaging Technologies  (Volume:23 ,  Issue: 4 )