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Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

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10 Author(s)
D. M. Brooks ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; P. Bose ; S. E. Schuster ; H. Jacobson
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The ability to estimate power consumption during early-stage definition and trade-off studies is a key new methodology enhancement. Opportunities for saving power can be exposed via microarchitecture-level modeling, particularly through clock-gating and dynamic adaptation. In this paper we describe the approach of using energy-enabled performance simulators in early design. We examine some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics

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IEEE Micro  (Volume:20 ,  Issue: 6 )