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Fast VLSI motion estimator based on bit plane matching

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4 Author(s)
Ko, Y.-K. ; Dept. of Electron. Eng., Korea Univ., Seoul, South Korea ; Kim, H.-G. ; Oh, H.-C. ; Ko, S.J.

A fast VLSI motion estimator based on bit plane matching is proposed. The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilise lower-cost fabrication technology

Published in:

Electronics Letters  (Volume:36 ,  Issue: 23 )