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Modeling and simulation of a sigma-delta digital to analog converter using VHDL-AMS

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3 Author(s)
Vogels, M. ; ESAT, Katholieke Univ., Leuven, Heverlee, Belgium ; De Smedt, B. ; Gielen, G.

Sigma-Delta digital to analog converters are less vulnerable to circuit imperfections than their A/D counterparts because they have their noise-shaping loop all in the digital domain. Still the analog part of the system (basically a low-pass filter) can degrade the overall performance, especially in the case of multi-bit converters. This paper presents a way of identifying and simulating the major noise and harmonics contributions of the system using VHDL-AMS. The resulting system-level model can be used to explore different architectures in the digital domain and to determine the specifications of the different building blocks

Published in:

Behavioral Modeling and Simulation, 2000. Proceedings. 2000 IEEE/ACM International Workshop on

Date of Conference:

2000