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Design of 3:1 multiplexer standard cell

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3 Author(s)
P. Corsonello ; Dept. of Comput. Sci., Univ. of Reggio Calabria, Italy ; S. Perri ; V. Kantabutra

A new VLSI 3:1 multiplexer is presented. The proposed circuit is based on a double controlled tri-state buffer. A custom cell which can easily be added to the AMS 0.6 μm CMOS standard cell library has been developed. The new cell shows a propagation delay of ~780 ps and dissipates 5.2 μW/MHz

Published in:

Electronics Letters  (Volume:36 ,  Issue: 24 )