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A packet-switched system architecture based on the combination of a single-chip output-buffered switch element and input queues that sort arriving packets on a per-output-port basis is proposed. Scheduling is performed in a distributed two-stage approach. Independent arbiters at each of the inputs resolve input contention. Whereas the output-buffered switch element resolves output contention. As a result of this distribution of functionality, complexity of the input arbiters is only linearly proportional to the number of output ports N, thus offering better scalability than purely input-buffered approaches that require complex centralized schedulers. Since the input queues are used as the main buffering mechanism, only a relatively small amount of memory (on the order of N/sup 2/ packet locations) is required in the shared-memory switch, allowing high-throughput implementations. We present simulation results to demonstrate the high performance and robustness under bursty traffic achieved with the proposed system architecture. A practical implementation in the form of the PRIZMA family of switch chips is outlined, with emphasis on its versatility in scaling in terms of both port speed and number of ports, and its support for quality-of-service mechanisms.