p-channel amorphous silicon TFTs with high hole mobility

The authors have fabricated p-channel FETs using a-Si:H(F) films, to demonstrate the high hole mobility of a-Si:H(F) in these devices as well as to investigate the feasibility of a-Si CMOS devices. To prepare high-quality a-Si films, a glow discharge of a gaseous mixture of SiF/sub 4/ and H/sub 2/ was used as a deposition precursor, and the residence time of the reactants was varied carefully for the preparation of relevant radicals. The authors fabricated a prototype p-channel MOSFET with a staggered electrode structure consisting of a 100 nm layer of a-Si:H(F), a 200-nm layer of CVD (chemical-vapor-deposited) SiO/sub 2/, and an evaporated-Cr film for source-drain and gate electrodes. In the final step, the device was annealed in H/sub 2/ for 30 min at 250 degrees C. The field-effect mobility for holes deduced from transistor characteristics was 0.12 cm/sup 2//V-s, about two orders higher than that of conventional p-channel a-Si FETs. An off-resistance/on-resistance ratio higher than 5000 has been obtained. The electron mobility was 0.24 cm/sup 2//V-s.<
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