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Design of a fault tolerant multistage interconnection network with parallel duplicated switches

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3 Author(s)
Kamiura, N. ; Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan ; Kodera, T. ; Matsui, N.

In this paper we propose a fault tolerant baseline network as a sort of MINs (multistage interconnection networks) and discuss its performance analysis. For our MIN with N input and N output terminals, switching elements in the first and n-th stages are duplicated where n=log2N. Four-input two-output switching elements and two-input four output ones employed in the second and (n-1)-th stages are useful in sharing loads efficiently on the first and n-th stages respectively. The comparison results show that the theoretical throughput of our MIN without faults and the performance of our MIN with faults are superior to those of previously known ELMIN though our MIN requires slightly more hardware overhead than ELMIN

Published in:

Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on

Date of Conference:

2000