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A high throughput FPGA implementation of a bit-level matrix product

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4 Author(s)
Amira, A. ; Sch. of Comput. Sci., Queen''s Univ., Belfast, UK ; Bouridane, A. ; Milligan, P. ; Sage, P.

This paper presents a novel architecture for a matrix product algorithm. The paper describes the mathematical model for the algorithm (based on the Baugh-Wooley algorithm), the associated design and implementation of the algorithm on a Xilinx FPGA board, and discusses the efficiency of the implementation. The architecture developed requires O(N2) and O(2nN) and O(N) and O(2nN) as area and time complexities respectively for the matrix-matrix product and matrix-vector product, respectively (where N is the matrix size and n is the word length)

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Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on

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