A high throughput FPGA implementation of a bit-level matrix product

This paper presents a novel architecture for a matrix product algorithm. The paper describes the mathematical model for the algorithm (based on the Baugh-Wooley algorithm), the associated design and implementation of the algorithm on a Xilinx FPGA board, and discusses the efficiency of the implementation. The architecture developed requires O(N/sup 2/) and O(2nN) and O(N) and O(2nN) as area and time complexities respectively for the matrix-matrix product and matrix-vector product, respectively (where N is the matrix size and n is the word length).