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Multi-level cache hierarchy evaluation for programmable media processors

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2 Author(s)
Fritts, J. ; Dept. of Comput. Sci., Washington Univ., St. Louis, MO, USA ; Wolf, W.

This paper presents the results of a multi-level cache memory hierarchy evaluation for programmable media processors. With the continuing advances in VLSI technology, it becomes possible to support larger memory hierarchies on-chip, but the question remains of how to most effectively use these additional silicon resources for optimizing memory performance. This paper explores that issue by evaluating the various levels of the memory hierarchy using a cache-based memory system. This evaluation examines the change in performance from varying cache parameters including the L2 cache parameters of cache size, line size, and latency, and the external memory parameters of bandwidth and latency. Examining the performance impact of these parameters, we have identified external memory latency and bandwidth as the primary memory bottlenecks in media processors

Published in:

Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on

Date of Conference:

2000