Low power 2-D array VLSI architecture for block matching motion estimation using computation suspension

We propose a low power 2-D array VLSI architecture for block matching motion estimation based on computation suspension. A portion of the processing elements can be disabled adaptively during the computation of the sum of absolute difference (SAD) of a candidate block when the partial SAD obtained so far is found larger than the current minimum SAD to save power. An efficient VLSI architecture which can support the redundancy detection and PE disabling with minimum overhead is developed. Experimental results show that more than 30% of power consumption reduction can be achieved by suspending unnecessary computations.