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Single-chip CMOS CCD camera interface based on digitally controlled capacitor-segment combination

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2 Author(s)
Tae-Hwan Oh ; Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea ; Seung-Hoon Lee

This work describes a single-chip solution for CMOS charge-coupled device (CCD) camera interface systems. The required gain of the automatic gain control circuit (AGC) in the proposed system is controlled directly by digital bits without conventional extra digital-to-analog (D/A) converters, and the signal-settling behavior is almost independent of AGC gain variations at video speeds. A capacitor-segment combination technique to implement large capacitances considerably improves the effective bandwidth of the AGC based on switched-capacitor techniques. A layout scheme minimizing truncation errors shows AGC matching accuracy better than 0.1%. Nonlinear errors such as offsets in signal paths are automatically measured during black-level correction. The outputs from the AGC are transferred to a 10 b analog-to-digital (A/D) converter integrated on the same chip. The prototype implemented in a 0.5 μm n-well CMOS process shows the 32 dB AGC dynamic range in 1/8-dB gain steps with 173 mW at 3 V and 25 MHz.

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:47 ,  Issue: 11 )