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With the spread of Reed-Solomon (RS) codes to portable wireless applications, low-power RS decoder design has become important. This paper discusses how the Berlekamp Massey decoding algorithm can be modified and mapped to obtain a low-power architecture. In addition, architecture level modifications that speed-up the syndrome and error computations are proposed. Then the VLSI architecture and design of the proposed low power/high-speed decoder is presented. The proposed design is compared with a normal design that does not use these algorithm/architecture modifications. The power reduction when compared to the normal design is estimated. The results indicate a power reduction of about 40% or a speed-up of 1.34.