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A 2-μm BiCMOS process utilizing selective epitaxy

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4 Author(s)
O, K.K. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA ; Lee, H.-S. ; Reif, R. ; Frank, W.

The authors describe a BiCMOS process that incorporates a high-performance n-p-n bipolar structure with a cutoff frequency (f T) of 5 GHz and an isolated nonoptimized vertical p-n-p bipolar structure to a 2-μm twin-well CMOS process with poly-to-n+ capacitors. These high-performance structures are incorporated with only two additional masking steps without affecting the performance of the NMOS and PMOS transistors of the original CMOS process. The device characteristics for the NMOS and PMOS transistors are similar to those of the MOS transistors of the original CMOS process. The device characteristics of the vertical n-p-n and p-n-p transistors, as well as the NMOS and PMOS transistors, are described

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Electron Devices, IEEE Transactions on  (Volume:35 ,  Issue: 12 )