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Monolithically integrated InGaAs PIN-InP JFET amplifier with high sensitivity

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4 Author(s)
Kim, S.J. ; AT&T Bell Lab., Murray Hill, NJ ; Guth, G. ; Vella-Coleiro, G.P. ; Seabury, C.W.

Results on a p-i-n diode (PIN)-FET amplifier fabricated with high-performance fully ion-implanted InP JFETs are presented. An undoped InGaAs absorption layer and an Fe-doped semi-insulating InP layer are grown on an n+InP substrate. A Zn diffusion using evaporated Zn3P2 and ion implantation are performed on the top layer to form the PIN and FETs, respectively. The fully ion-implanted InP JFET has a transconductance over 100 mS/mm at V gs=0 with a 3-dB cutoff frequency of about 9 GHz. A complete preamplifier is implemented, consisting of gain and level-shifting buffer stages with an open-loop voltage gain of 5.5. The amplifier uses a novel symmetrical design in which the DC offset is zero at the output. A receiver sensitivity of -36.4 dBm is measured from the integrated PIN-JFET amplifier for 200 Mb/s NRZ (nonreturn-to-zero) optical signals (1.3-μm wavelength) at 1×10-9 bit error rate. To the authors' knowledge, this is the best sensitivity reported for a PIN-FET device designed for the 1.3-1.55 μm wavelength region

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Electron Devices, IEEE Transactions on  (Volume:35 ,  Issue: 12 )