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Low-speed scan testing of charge-sharing faults for CMOS domino circuits

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4 Author(s)
C. H. Cheng ; Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Taiwan ; W. B. Jone ; S. C. Chang ; J. S. Wang

Domino circuits have been widely used to design high-performance processors. However, domino logic suffers from the problem of charge-sharing, which may degrade the output voltage level or even cause an erroneous output value (charge-sharing fault). It is shown that charge-sharing faults are resistant to scan testing and that a killing error might occur because of the low-speed testing problem caused by scan testing. The testing error is investigated and a DFT technique to efficiently eliminate this problem is proposed

Published in:

Electronics Letters  (Volume:36 ,  Issue: 20 )