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Improved linear systolic array for fast modular exponentiation

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1 Author(s)
Walter, C.D. ; Comput. Dept., Univ. of Manchester Inst. of Sci. & Technol., UK

Due to the large word lengths involved, communication and buffering are potentially the major problems in implementing the modular arithmetic used in several cryptosystems. It is shown here how a single, linear systolic array eliminates much of the associated overheads, thereby improving throughput and the ratio of speed to area for modular exponentiation. Alternative forms produce simpler processing elements and make fuller use of the hardware, making it more easily implemented in current technology. Such designs are regarded as much safer for use in smartcards and embedded systems as they offer greater protection against attacks using differential power analysis. A 1024-bit array can be built in an area comparable to a 64-bit multiplier

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:147 ,  Issue: 5 )

Date of Publication:

Oct 2000

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