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Efficient parallel adder based design for one-dimensional discrete cosine transform

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1 Author(s)
Guo, J.-I. ; Dept. of Electron. Eng., Nat. Lien-Ho Inst. of Technol., Miao-Li, Taiwan

The author proposes an efficient parallel adder based design for the one-dimensional (1-D) discrete cosine transform (DCT). A new algorithm is developed that exploits the merits of cyclic convolution to facilitate the realisation of a 1-D any-length DCT using parallel adders. Based on this algorithm, the proposed design possesses the advantages of low hardware cost, low input/output (I/O) cost, high computing speed, and high flexibility in transform length. Considering an example using 16-bit coefficients, the proposed design can save about 58% and 80% of the gate area, as compared with the distributed arithmetic (DA)-based designs, for the 64 and 128 transform lengths, respectively

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:147 ,  Issue: 5 )