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The design and implementation of a low-power clock-powered microprocessor

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9 Author(s)
Athas, W. ; House Ear Inst., Los Angeles, CA, USA ; Tzartzanis, N. ; Mao, W. ; Peterson, L.
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We describe the design and implementation of a 16-bit clock-powered microprocessor that dissipates only 2.9 mW at 15.8 MHz based on laboratory measurements. Clock-powered logic (CPL) has been developed as a new approach for designing and building low-power VLSI systems that exploit the benefits of supply-voltage-scaled static CMOS and energy-recovery CMOS techniques. In CPL, the clock signals are a source of ac power for the other large on-chip capacitive loads. Clock amplitude and waveform shape combine to reduce power. By exploiting energy recovery and an energy-conserving clock driver, it is possible to build ultra-low-power CMOS processors with this approach. We compare the CPL approach with a conventional, fully dissipative approach for a processor with a similar ISA and VLSI architecture which was designed using the same set of VLSI CAD tools. The simulation results indicate that the CPL microprocessor would dissipate 40% less power than the conventional design.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 11 )

Date of Publication:

Nov. 2000

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