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Residue arithmetic VLSI array architecture for manipulator pseudo-inverse Jacobian computation

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2 Author(s)
Chang, Po Rong ; Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA ; Lee, C.S.G.

The authors present the design of a two-level macro-pipelined VLSI array architecture for the real-time computation of the exact solution of the manipulator pseudo-inverse Jacobian using the Decell algorithm in the residue arithmetic system. The first-level arrays are asynchronous data-driven, wave-front-like arrays and perform matrix multiplication, matrix diagonal addition, and trace computations in the Decel algorithm. A pool of the first-level arrays is then configured into a second-level macro-pipeline with outputs of one array acting as inputs to another array in the pipe. The pipelined time of the proposed two-level pipelined array architecture has a computational order of 0(n+2 p-1), which is the same computational complexity order as that of the evaluation of a matrix product in an ordinary wavefront array. For a 12 degree-of-freedom redundant robot, a pipelined time of 6.975 μs is achievable with current VLSI custom design technology

Published in:

Robotics and Automation, IEEE Transactions on  (Volume:5 ,  Issue: 5 )

Date of Publication:

Oct 1989

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