By Topic

A complete model for glitch analysis in logic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ki-Seok Chung ; Synopsys Inc., Mountain View, CA, USA ; Taewhan Kim ; Liu, C.L.

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many such switching activities are due to spurious pulses, called glitches. Recently, a new model of glitch analysis, called G-vector has been proposed. The power of the model is that, unlike the existing ones which model only the propagation of glitches to count the number of glitches in the circuits, it allows one to model the generation, propagation and elimination of glitches to be able to not only count the number of glitches but also locate the glitches. In this paper, we complete the concept of G-vector by providing a set of efficient solutions to the two important practical issues: (1) extending to signals over multiple clock cycles, and (2) extending to a logic decomposition utilizing the model. Integrating the solutions all together enables G-vector to be very efficient. A set of experimental results is provided to show the effectiveness of the proposed solutions

Published in:

ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International

Date of Conference:

2000