By Topic

A modular VLSI architecture for real-time processing of video streaming applications over ATM network

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Doumenis, Gr. ; Dept. of Electr. Eng., Nat. Tech. Univ. of Athens, Greece ; Konstantoulakis, G. ; Korinthios, G. ; Lykakis, G.
more authors

This paper presents a VLSI architecture specifically designed to support emerging video/data communication/multiplexing applications as a video/communication controller in an ATM network. Using a shared memory with efficient interconnection the design can accommodate either a processing system as a peripheral which can store data and perform specific operations on these, or a switching system as a buffer with real time processing and multiplexing capabilities. The architecture consists of three (3) processing modules, a shared memory with four (4) banks and two (2) input/output modules. The design can operate at a data transfer speed of 622 Mbit/sec. Per flow queuing, implemented in shared memory, supports shaping and multiplexing operations on data, on a process/connection basis. The design is capable of multiplexing thousands of flows performing shaping according to a traffic profile for each flow. Traffic profiles could be either static according to negotiable network parameters or dynamic in applications, such as video transport, where a connection presents diversity in bandwidth allocation requirements. Dynamic update of traffic profiles involves real-time measurements and calculations of incoming packets. These operations are efficiently mapped in hardware/software components, inside the processing modules, implementing the respective algorithms. Performance trials of the design have indicated that the behaviour of the controller under heavy load improves with the use of the appropriate algorithms. The architecture embeds both the processing and the memory modules, thus producing a true system-on-a-chip solution

Published in:

Electrotechnical Conference, 2000. MELECON 2000. 10th Mediterranean  (Volume:1 )

Date of Conference: