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Array processors for DSP: implementation considerations

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3 Author(s)
M. Zajc ; Lab. for Digital Signal Process., Ljubljana Univ., Slovenia ; R. Sernec ; J. Tasic

Modern DSP applications depend on high throughput and massive data used in computations. Array processors present an appealing approach of parallelism exploitation for meeting real-time requirements. The intention of the paper is to address the potential of a fixed interconnection topology systolic array as well as alternative implementation approaches for reconfigurable topology systolic arrays. Our work is merely limited to array processors that work in a so-called systolic manner.

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Electrotechnical Conference, 2000. MELECON 2000. 10th Mediterranean  (Volume:2 )

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