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Modeling hot-carrier effects in polysilicon emitter bipolar transistors

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2 Author(s)
J. D. Burnett ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA ; Hu Chenming

In self-aligned polysilicon emitter transistors a large electric field existing at the periphery of the emitter-base junction under reverse bias can create hot-carrier-induced degradation. The degradation of polysilicon emitter transistor gain under DC stress conditions can be modelled by ΔIBIR m+ntn where n≈0.5 and m ≈0.5. The more complex relationships of Δβ(I C, IR, t) and β(I C, IR, t) result naturally from the simple ΔIB model. Using these relationships the device lifetime can be extrapolated over a wide range of reverse stress currents for a given technology

Published in:

IEEE Transactions on Electron Devices  (Volume:35 ,  Issue: 12 )