By Topic

One trillion operations per second on-board VLSI signal processor for Discoverer II space based radar

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Song, W.S. ; Lincoln Lab., MIT, Lexington, MA, USA ; Baranoski, E.J. ; Martinez, D.R.

A high-performance low-power radar signal processor is being developed for the Discoverer II space-based radar application. The signal processor will perform real-time ground moving target indication (GMTI) and synthetic aperture radar (SAR) front-end signal processing functions, which significantly reduces the downlink communication bandwidth. In order to minimize the signal dispersion, the wideband receive signal is first channelized into multiple digital subbands and all the subsequent processing tasks including beamforming, pulse compression, and space-time adaptive processing (STAP) are done in the subband domain. In order to meet over one trillion operations per second (Teraops) computational throughput requirement with low power consumption and small form factor, a highly optimized scalable VLSI bit-level systolic array technology is used. The 1 Teraops on-board processor is currently projected to consume less than 50 watts and to be less than 1/8 cubic foot and 12 kg

Published in:

Aerospace Conference Proceedings, 2000 IEEE  (Volume:5 )

Date of Conference:

2000