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One trillion operations per second on-board VLSI signal processor for Discoverer II space based radar

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3 Author(s)
W. S. Song ; Lincoln Lab., MIT, Lexington, MA, USA ; E. J. Baranoski ; D. R. Martinez

A high-performance low-power radar signal processor is being developed for the Discoverer II space-based radar application. The signal processor will perform real-time ground moving target indication (GMTI) and synthetic aperture radar (SAR) front-end signal processing functions, which significantly reduces the downlink communication bandwidth. In order to minimize the signal dispersion, the wideband receive signal is first channelized into multiple digital subbands and all the subsequent processing tasks including beamforming, pulse compression, and space-time adaptive processing (STAP) are done in the subband domain. In order to meet over one trillion operations per second (Teraops) computational throughput requirement with low power consumption and small form factor, a highly optimized scalable VLSI bit-level systolic array technology is used. The 1 Teraops on-board processor is currently projected to consume less than 50 watts and to be less than 1/8 cubic foot and 12 kg

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Aerospace Conference Proceedings, 2000 IEEE  (Volume:5 )

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