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Assignment-space exploration approach to concurrent data-path/floorplan synthesis

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3 Author(s)
Oohashi, K. ; Sch. of Inf. Sci., Japan Adv. Inst. of Sci. Technol., Japan ; Kaneko, M. ; Tayu, S.

As the geometrical design rules of VLSIs become finer into the order of deep sub-micron, the impact of wires to VLSI performance becomes larger relatively to the other components, and their estimation at RT-level description and performance-driven datapath synthesis need explicit connectivity information about RT-level architecture and its floorplan. In this paper, an assignment-driven approach to the datapath synthesis incorporated with one-dimensional floor planning is proposed. In our approach, scheduling and one-dimensional floorplanning, both of which are driven by iteratively generated functional unit and register assignment (binding), are performed fully concurrently. Pseudo-branch-and-bound assignment space exploration is adopted for generating assignments in this pilot system

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Computer Design, 2000. Proceedings. 2000 International Conference on

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