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Application of a systolic macrocell-based VLSI design style to the design of a single-chip high-performance FIR filter

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4 Author(s)
Roncella, R. ; Centro di Studio per Metodi e Dispositivi per Radiotrasmissioni, Pisa, Italy ; Saletti, R. ; Terreni, P. ; Piatelli, D.

Presents the application of a VLSI design style based on systolic macrocells in the realisation of a single-chip high-performance digital FIR filter. The systolic macrocell design style is well suited for the design of high-performance integrated circuits to be used in digital signal processing. The style uses as design primitives bit-level systolic macrocells designed according to logical and electrical rules that guarantee the required performance. The filter was designed with a 1.5 μm CMOS technology; it occupies an area of 3.74×3.42 mm2 and has 128 coefficients. The expected clock frequency is of about 100 MHz and allows a throughput of the order of 1 million samples per second. The technique applied to the design of the most critical part of the circuit (the clock generation and distribution network) is also described

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Circuits, Devices and Systems, IEE Proceedings G  (Volume:138 ,  Issue: 1 )