Cart (Loading....) | Create Account
Close category search window
 

An analytical model for current, delay, and power analysis of submicron CMOS logic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hamoui, A.A. ; Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada ; Rumin, N.C.

An analytical model for computing the supply current, delay, and power of a submicron CMOS inverter is presented. A modified version of the nth power law MOSFET model is proposed and used to relate the terminal voltages to the drain current in submicron transistors. By first computing definable reference points on the output voltage waveform, and then using linear approximations through these points to find the actual points of interest, the desired speed and accuracy of the inverter model are achieved. The most important part of the analysis is a three-step approach for computing the time and output voltage when the short-circuit transistor changes its mode of operation. The time and output voltage when the charging/discharging current reaches its maximum are also calculated and then used to evaluate the propagation delay and characterize the output voltage waveform. The model has been validated for both 0.8 μm (5 V) and 0.25 μm (2.5 V) CMOS technologies, for a wide range of inverter sizes, input transition times, and capacitive loads. It predicts the delay, peak supply current, and power dissipation to within a few percent of HSPICE or ELDO simulations based on accurate physically based MOSFET models, while offering about two orders of magnitude gain in CPU time based on a MATLAB implementation

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:47 ,  Issue: 10 )

Date of Publication:

Oct 2000

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.