By Topic

Single electron memory utilizing nano-crystalline Si over short-channel silicon-on-insulator transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Hinds, B.J. ; Res. Center for Quantum Effect Electron., Tokyo Inst. of Technol., Japan ; Dutta, A. ; Yun, F. ; Yamanaka, T.
more authors

A promising approach for high density/low power consumption memory devices is to store a single charge in a nano-scale memory node, which affects electron transport in a nearby channel. Advantages of this design are room temperature operation and self limiting charge storage by Coulomb repulsion. Two notable approaches to this concept are nanocrystalline-Si (nc-Si) acting as a floating gate in a large area MOSFET (Tiwari et al., 1996) and a single polysilicon dot defined by e-beam lithography over a narrow SOI channel (Guo et al., 1997). A device which is sensitive to a single charge while using a method of nc-Si dot fabrication that is scalable to VLSI is required. Single electron memory devices based on two approaches of forming nc-Si with large area deposition processes are reported here. To make the active region of the device sensitive to a single charged dot, narrow channels (40 nm length by 30 nm width) are defined by e-beam lithography of thin (20 nm) SOI. The first approach for nc-Si synthesis is gas phase nucleation and growth by pulsed-source remote PECVD, which form 8/spl plusmn/1 nm diameter nc-Si dots (Ifuku et al., 1997). The second approach for scalable nc-Si formation is to deposit a thin film of SiO/sub x/ (x<2). Annealing of this film results in high density 3-8 nm nc-Si dots isolated from each other by a SiO/sub 2/ tunnel barrier (Hamasaki et al., 1978).

Published in:

Device Research Conference, 2000. Conference Digest. 58th DRC

Date of Conference:

19-21 June 2000