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Gate capacitance has complex voltage dependency on terminal voltages but the impact of this voltage dependency of gate capacitance on power and delay has not been fully investigated, especially, in low-voltage, low-power designs. Introducing an effective gate capacitance, CG,eff it is shown that the power and delay of CMOS digital circuit can be estimated accurately. CG,eff is a strong function of VTH/VDD and VTH/VDD tends to increase in low-voltage region. Hence, the effective capacitance relative to oxide capacitance, COX, is decreasing in low-voltage, low-power designs. Therefore, considering CG,eff in accurate power and delay estimation becomes more important in the future.