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A low-voltage CMOS multiplier for RF applications

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3 Author(s)
Debono, C.J. ; Dept. of Electron., Pavia Univ., Italy ; Maloberti, F. ; Micallef, J.

A low-voltage analog multiplier operating at 1.2 V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6 μm CMOS technology. Simulation results indicate an IP3 of 4.9 dBm and a spur free dynamic range of 45 dB.

Published in:

Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

Date of Conference:

2000

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