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Low power self-timed radix-2 division

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2 Author(s)
Jae-Hee Won ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Kiyoung Choi

A self-timed radix-2 division scheme for low power consumption is proposed. By replacing dual-rail dynamic circuits in non-critical data paths with single-rail static circuits, power dissipation is decreased, yet performance is maintained by speculative remainder computation. SPICE simulation results show that the proposed design can achieve 33.8-ns latency for 56-bit mantissa division and 47% energy reduction compared to a fully dual-rail version.

Published in:

Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

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