Skip to Main Content
This paper describes an adaptive power management architecture to reduce power consumption in digital filters. The proposed approach combines two low-power techniques which utilize supply voltage reduction. The first technique, multiple voltage distribution (MVD), attempts to reduce power consumption by assigning reduced supply voltages to circuit modules while satisfying timing constraints. The second technique, adaptive voltage scaling (AVS), dynamically adjusts these multiple voltages to meet throughput requirements resulting in further power reduction. An FIR filter application using the combined MVD-AVS power management scheme for two adaptively scaled supply voltages is shown to consume one-third the power of a fixed supply voltage scheme, and half the power consumed with a single supply AVS.