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Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation

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8 Author(s)
Hamzaoglu, F. ; Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA ; Yibin Ye ; Keshavarzi, A. ; Zhang, K.
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Comparisons among different dual-VT design choices for a large on-chip cache with single-ended sensing show that the design using a dual-VT cell and low-VT peripheral circuits is the best, and provides 10% performance gain with 1.2x larger active leakage power, and 1.6% larger cell area compared to the best design using high-VT cells.

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Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

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