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A SONET STS-3c user network interface integrated circuit

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2 Author(s)
T. J. Robe ; Bellcore, Red Bank, NJ, USA ; K. A. Walsh

Two different design implementation techniques were used to produce a functionally complex high performance synchronous optical network (SONET) synchronous transmission signal (STS)-3c (155.52 Mb/s) user network interface (UNI) chip in cost-effective 1 μm CMOS technology. The CMOS chip functions as an STS-3c transmitter and receiver and can interface to the STS-3c line in either bit-serial or byte-parallel data format. The transmitter creates a SONET STS-3c frame structure including the necessary framing and control bytes. The receiver performs frame detection, several performance monitoring functions, and payload processor interpretation. In addition to SONET overheads, both the transmitter and receiver provide payload asynchronous transfer mode (ATM) mapping signals to the user. The user can choose between serial operation at 155.52 Mb/s or parallel operation at 19.44 Mbyte/s. Test results show that the experimental integrated circuit performs successfully at serial data rates of up to 300 Mb/s

Published in:

IEEE Journal on Selected Areas in Communications  (Volume:9 ,  Issue: 5 )