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High-speed Si-bipolar IC design for multi-Gb/s optical receivers

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7 Author(s)
H. Hamano ; Fujitsu Lab. Ltd., Kawasaki, Japan ; T. Yamamoto ; Y. Nishizawa ; A. Tahara
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The authors developed several special circuits to minimize the decrease in speed caused by parasitics. The common-base circuit assures flat and wide frequency preamplifier response even when Vee is unstable because of bond wire inductance. Cascode interconnections between circuit blocks prevent waveform degradation due to line capacitance discharge. The high level of integration prevents the signal speed from decreasing due to chip interfaces and external interference. Using these circuits and Si-bipolar ESPER (emitter-base self-aligned structure with polysilicon electrodes and resistors) transistors whose fT was 28 GHz, the authors fabricated three ICs: a preamplifier with a 5.1 GHz bandwidth, a fully integrated automatic gain control (AGC) amplifier with a 3.6 GHz bandwidth, and a decision circuit that operates at 10.6 Gb/s. The authors used these ICs and an avalanche photodiode (APD) to construct a 5 Gb/s optical receiver with a minimum detectable optical power of -26.8 dBm. The speed of the Si ICs exceeded 5 Gb/s

Published in:

IEEE Journal on Selected Areas in Communications  (Volume:9 ,  Issue: 5 )