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An integrated circuit for the in situ characterization of CMOS best-process micromachining

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2 Author(s)
Warneke, B. ; Berkeley Sensor & Actuator Center, California Univ., Berkeley, CA, USA ; Pister, K.S.J.

We have developed an integrated circuit for in situ monitoring and characterization of CMOS post-process micromachining. In our demonstration, the circuit provides automated readout of N-well resistors surrounding each of 140 micromachining test structures at up to 14,000 samples per second per device during the post-process silicon etch. We use this circuit to examine the effect of pit size, surrounding thin film layers, and topography in a 2 μm CMOS process with a XeF 2 post-process step, although the circuit and results are of use to EDP, TMAH, and plasma post-processing

Published in:

Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on

Date of Conference:

2000

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