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Group delay as an estimate of delay in logic

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5 Author(s)
Vlach, J. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Barby, J.A. ; Vannelli, A. ; Talkhan, T.
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It is an accepted practice in signal delay estimation to model MOS digital circuits as RC circuits. In most cases Elmore's definition is exactly equivalent to the group delay of the network at zero frequency. A computationally efficient noniterative method to calculate this delay for networks with any linear elements and arbitrary topology is presented. It is shown that in RC networks under certain conditions, the Elmore delay and the 50% unit step response delay are related by a constant which is largely independent of the element values and topology. An efficient method to obtain sensitivities of the delay with respect to any element in the network is presented

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:10 ,  Issue: 7 )

Date of Publication:

Jul 1991

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