Modeling of short circuit power consumption using timing-only logic cell macromodels

This paper proposes an analytical modeling of power consumption in CMOS gates which is based on timing-only models. The proposed model is refined for the short circuit power dissipation as a function of input transition times, power supply voltage and output loading (C/sub L/) factor. The influence of the short circuit power dissipation can introduce an error of up to 25% in the average of dynamic power estimation. In this paper we model correctly this effect, with a minimum increase in the complexity of the model. Moreover, the same model used for timing analysis purposes can be used to investigate the total power consumption, including short circuit dissipation. The formulation is geared toward cell-oriented logic synthesis, which handles delays and signal slopes. The work shows the model connection between power components and the timing parameters computed at the switch or logic level. Results are presented showing the short circuit component as a fraction of total power for gates and circuits like buffers and adders.