By Topic

Easily testable gate-level and DCVS multipliers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Takach, A.R. ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; Jha, N.K.

Some C-testable designs of a carry-save parallel multiplier are presented. Results are given for both the gate-level implementation and the differential cascode voltage switch (DCVS) implementation. DCVS circuits are dynamic CMOS circuits which have the advantage of being protected against test set invalidation due to circuit delays. In the first gate-level design, it is assumed that the full-adders have any arbitrary, irredundant logic implementation. Such a design is C-testable with only nine test vectors, which detect all single stuck-at-faults. For a specific logic implementation of the full-adders, another design is shown to be C-testable with only six test vectors. The DCVS design is also C-testable with only six test vectors, which detect all detectable stuck-at, and stuck-open faults in the circuit. Both the hardware and delay overhead for all C-testable designs are very small. For three C-testable designs of the 32 by 32 multiplier, the hardware overhead is 2.7% or less and the delay overhead is 2.4% or less

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:10 ,  Issue: 7 )