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Easily testable gate-level and DCVS multipliers

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2 Author(s)
A. R. Takach ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; N. K. Jha

Some C-testable designs of a carry-save parallel multiplier are presented. Results are given for both the gate-level implementation and the differential cascode voltage switch (DCVS) implementation. DCVS circuits are dynamic CMOS circuits which have the advantage of being protected against test set invalidation due to circuit delays. In the first gate-level design, it is assumed that the full-adders have any arbitrary, irredundant logic implementation. Such a design is C-testable with only nine test vectors, which detect all single stuck-at-faults. For a specific logic implementation of the full-adders, another design is shown to be C-testable with only six test vectors. The DCVS design is also C-testable with only six test vectors, which detect all detectable stuck-at, and stuck-open faults in the circuit. Both the hardware and delay overhead for all C-testable designs are very small. For three C-testable designs of the 32 by 32 multiplier, the hardware overhead is 2.7% or less and the delay overhead is 2.4% or less

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:10 ,  Issue: 7 )