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Fast batch incremental netlist compilation hierarchical schematics

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1 Author(s)
Jones, L.G. ; Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA

Fast batch and incremental algorithms for creating and updating the netlist underlying a hierarchical schematic design are presented. The algorithms can be used either for maintaining the netlist as a data structure for further online processing or as a file for use with other offline design tools that are downstream from the compilation process. The batch algorithm uses a preorder traversal of the design hierarchy to derive the netlist. The incremental algorithm trims this traversal to only those paths leading to changes in the netlist. For most user modifications the netlist can be incrementally updated in a fraction of the time required using batch compilation techniques, often with no perceivable delay to the user

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:10 ,  Issue: 7 )