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A new methodology for the design centering of IC fabrication processes

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2 Author(s)
K. K. Low ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; S. W. Director

The authors describe a practical methodology that can be applied to optimize the process yield of IC fabrication lines. The yield maximization problem is first reformulated into a deterministic design centering problem. Macromodeling and problem decomposition are then applied to solve the design centering problem efficiently. The effectiveness of this methodology is illustrate through a simulation example involving a CMOS process adopted from an industrial line

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:10 ,  Issue: 7 )