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IBM RISC System/6000: architecture and performance

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2 Author(s)
R. R. Oehler ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; M. W. Blasgen

The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional units, avoid dead cycles, and define instructions that can (for the most part) be completed at a rate of one per cycle. The branch cycle, fixed- and floating-point units, cache management, and performance are described. Benchmark results are given.<>

Published in:

IEEE Micro  (Volume:11 ,  Issue: 3 )