Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Memory architecture for parallel line drawing based on non incremental algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Marti, P.M. ; Dept. of Autom. Control & Comput. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain ; Velasco, A.B.M.

This paper presents a parallel VLSI architecture for fast line drawing. The architecture implements a non incremental line drawing algorithm which allows to write simultaneously in a memory array all the pixels that approximate the straight segments. This paper explains the bottom-zip process for a simplified architecture design that reduces the circuitry redundancies in order to minimize the area. This memory architecture also provides read/write random accesses and raster outputs that permit the memory architecture to display the data serially. A 256×256 eight-bit pixel processor array has been designed using a 0.35 μm standard cells. An exhaustive test and simulation results upon this design have demonstrated that a rate of 50 M segments per second can be achieved, independently of their length and orientation

Published in:

Euromicro Conference, 2000. Proceedings of the 26th  (Volume:1 )

Date of Conference:

2000