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Memory architecture for parallel line drawing based on non incremental algorithm

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2 Author(s)
Marti, P.M. ; Dept. of Autom. Control & Comput. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain ; Velasco, A.B.M.

This paper presents a parallel VLSI architecture for fast line drawing. The architecture implements a non incremental line drawing algorithm which allows to write simultaneously in a memory array all the pixels that approximate the straight segments. This paper explains the bottom-zip process for a simplified architecture design that reduces the circuitry redundancies in order to minimize the area. This memory architecture also provides read/write random accesses and raster outputs that permit the memory architecture to display the data serially. A 256×256 eight-bit pixel processor array has been designed using a 0.35 μm standard cells. An exhaustive test and simulation results upon this design have demonstrated that a rate of 50 M segments per second can be achieved, independently of their length and orientation

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Euromicro Conference, 2000. Proceedings of the 26th  (Volume:1 )

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