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We report on the design, characterization, and page-oriented read demonstration of a 5/spl times/5 photoreceiver array fabricated within the technology constraints of a standard 1.2-/spl mu/m CMOS fabrication process. These monolithic circuits include a silicon-based photodetector, a multistage current amplifier, and a thresholding circuit that allows the photoreceiver sensitivity to be tuned over a wide range of optical power levels. In addition to characterizing the performance of individual photoreceiver circuits, we demonstrate the ability to interface directly with very large scale integration logic circuits. Finally, a 5/spl times/5 photoreceiver array is used to detect and then display a two-dimensional pattern of bits arranged in a page-oriented data format.
Date of Publication: Sept. 2000