By Topic

Mapping array communication onto FIFO communication - towards an implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kang, J. ; Philips Res. Lab., Eindhoven, Netherlands ; Van Der Werf, A. ; Lippens, P.

In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation of such applications is mostly FIFO (first-in, first-out) based. Mapping array communication onto a FIFO-based implementation requires complex address generators if the arrays have multiple dimensions. In this paper, we present a method for mapping array communication onto an efficient microcomputer architecture implementation based on FIFO communication via shared memory. A good hardware/software partitioning for the address generation is proposed. Furthermore, a complete design flow from specification to implementation is described. We illustrate this method with a design case: the communication of video frames between the front-end and the compressor in an MPEG encoder

Published in:

System Synthesis, 2000. Proceedings. The 13th International Symposium on

Date of Conference:

2000